1. Field of the Invention
The present invention relates to a layout evaluating apparatus for evaluating the feasibility of a layout of a circuit based on logic information such as a netlist, etc. prior to a layout design.
2. Description of the Related Art
In recent years, the scale and the density of an LSI have been increasing with the advance of manufacturing technologies, etc. Therefore, it has become vital to fully secure a layout process in the design process of an LSI.
The logic of an LSI peripheral to a CPU (hereinafter referred to as a peripheral LSI) significantly varies by generation unlike the arithmetic circuit of a CPU, etc. Accordingly, a block size by which a layout is made possible must be newly decided each time the logic varies.
However, since a considerable amount of time is required for the logic design process of a peripheral LSI due to an increase in the scale and the density of an LSI as described above, the stability of a netlist also requires a considerable amount of time. For this reason, a technique, with which the feasibility of a layout can be evaluated with short TAT (Turn Around Time: design/development duration) as soon as a netlist is created, becomes important.
If such an evaluation cannot be made, the feasibility of a layout is sometimes proved to be difficult at a stage of a layout process, for example, at a stage where the process proceeds to wiring operations. If such a case occurs, a logic design or a floor plan can be possibly changed, and a development schedule can be possibly behind.
Japanese Published Unexamined Patent Application No. H07-056982 discloses a layout method and a layoutability evaluating apparatus, which can shorten a layout time by evaluating the degree of difficulty of a layout of a designed circuit.
Additionally, Japanese Published Unexamined Patent Application No. 2000-076321 discloses an LSI design system and an LSI design method thereof, which grasp a chip size and a critical path in the initial stage of a design, and create a model of a functional block for an improvement.
Furthermore, in recent years, a technique for determining the degree of ease of a layout by creating an index from a netlist has been invented as disclosed by P. Kudva, A. Sullivan and W. Dougherty, “Metrics for Structural Logic Synthesis”, Proc. of ICCAD, pp. 551-556, 2002, or Q. Liu, M. M. Sadowska, “Pre-layout Wire Length and Congestion Estimation”, Proc. of DAC, pp. 582-587, 2004.